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6.25 Gbps, 4 x 4, Digital Crosspoint Switch with EQ AD8156
FEATURES
4 x 4, fully differential, nonblocking array Configurable for dual 2 x 2 operation DC to 6.25 Gbps per channel, NRZ data rate Programmable input equalization compensates for over 40" of FR-4 at 6.25 Gbps Multicast and broadcast modes of operation Programmable output swing 100 mV p-p to 1.6 V p-p differential Power supply: 3.3 V (10%) Low power No EQ: 400 mW typical Maximum EQ: 700 mW typical Inputs: ac-coupled or dc-coupled Wide set of dc-coupled input standards 3.3 V/2.5 V/1.8 V CML or 3.3 V LVPECL Control: LVTTL- or LVCMOS-compatible Low additive jitter: 25 ps p-p typical Low random jitter: 0.8 ps rms Integrated 50 termination impedance at inputs/outputs Individual output disable for power savings 49-ball, 8 mm x 8 mm BGA, 1 mm pitch
FUNCTIONAL BLOCK DIAGRAM
INPUT RECEIVERS IN0P/N INPUT EQUALIZATION EQ
AD8156
OUTPUT DRIVERS OUT0P/N
IN1P/N IN2P/N
EQ
4x4 SWITCH
OUT1P/N OUT2P/N
EQ
IN3P/N
EQ
OUT3P/N
Figure 1.
APPLICATIONS
Backplane equalization SONET/SDH Gigabit Ethernet XAUI Fibre Channel
GENERAL DESCRIPTION
The AD8156, a member of the Xstream line of products, is a high speed, fully differential, digital crosspoint switch. The part can function as a 4 x 4 crosspoint switch with double-latched memory, allowing simultaneous updates, or as a dual 2 x 2 with direct output control. The AD8156 has low power dissipation, typically 700 mW on 3.3 V with all outputs and input equalizers active. It operates at any data rate from dc to 6.25 Gbps per port. Each input channel on the AD8156 has a programmable input equalizer to compensate for signal loss over a backplane. The AD8156 high speed inputs are compatible with both accoupled and dc-coupled 3.3 V, 2.5 V, or 1.8 V CML, as well as 3.3 V LVPECL data levels. The control interface is LVTTL- and LVCMOS-compatible at 3.3 V. All input and output termination resistors are integrated for ease of layout and to minimize impedance mismatch. Input equalization and unused outputs can be individually disabled to minimize power dissipation. The AD8156 is packaged in a 49-ball, 8 mm x 8 mm, BGA package with a 1 mm ball pitch. It operates over the industrial temperature range of -40C to 85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06305-001
CS RST UPD WE RE MODE 4 D[3:0] 4 A[3:0]
CONTROL LOGIC
AD8156 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Specifications............................................................... 3 Timing Specifications .................................................................. 4 Timing Diagrams.............................................................................. 5 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Test Circuit ...................................................................................... 12 Theory of Operation ...................................................................... 13 4 x 4 Mode................................................................................... 13 Dual 2 x 2 Mode......................................................................... 13 Input Equalization...................................................................... 14 Control Interface Description....................................................... 15 Control Pins ................................................................................ 15 Address Pins, A[3:0] Inputs ...................................................... 16 Data Pins, D[3:0] Inputs/Outputs ............................................ 16 Control Interface Levels ............................................................ 16 Programming Examples ................................................................ 17 Dual 2 x 2 Mode (MODE Pin = 1) Programming Examples ............................................................ 17 4 x 4 Mode (MODE Pin = 0) Programming Examples ........ 17 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
5/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8156 SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VTTI = VTTO = VCC = 3.3 V, VEE = 0 V, RL = 50 , differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223-1, VIN = 1 V p-p differential, TA = 25C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Maximum Data Rate Deterministic Jitter Random Jitter Propagation Delay Propagation Delay Match Output Fall Time Output Rise Time INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Voltage Range Input Termination OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range Output Termination POWER SUPPLY VCC Operating Range Supply Current Symbol Conditions NRZ data Data date < 6.25 Gbps tPD tF tR VIN VCM RIN VOUT ROUT VCC ICC 1 ICC1 ICC1 ITTI ITTO Input to output Differential, 20% to 80% Differential, 20% to 80% Differential Single-ended Common-mode Single-ended Differential, programmable Common-mode Single-ended VEE = 0 V All disabled All outputs on, no equalization All outputs and equalizers on 800 mV differential swing 800 mV differential swing All disabled All outputs on, no equalization All outputs and equalizers on 200 VEE + 1.5 VEE + 1.6 50 50 VEE + 1.6 800 50 3.0 3.3 19 67 141 32 32 60 400 700 3.6 1850 VCC Min 6.25 25 0.8 1000 50 75 75 2000 VCC VCC Typ Max Unit Gbps ps p-p ps rms ps ps ps ps mV p-p V V mV p-p V V mA mA mA mA mA mW mW mW C V V
Power Dissipation 2
THERMAL CHARACTERISTICS Operating Temperature Range LOGIC INPUT CHARACTERISTICS Input VIN High Input VIN Low
1
-40 VCC = 3.3 V dc 2.0 0 VCC
85
0.8
2
ICC supply current excludes input and output termination currents. Currents at VTTI and VTTO count in power dissipation, but are not included in ICC. Note that in a CML output structure with separate termination supplies, all of the output and input current is drawn from VTTI and the termination resistors, not from Vcc. Power dissipation includes power due to 800 mV p-p differential input and output voltages; this is the true representation of power dissipated on and used by the chip at an 800 mV p-p differential signal level.
Rev. 0 | Page 3 of 20
AD8156
TIMING SPECIFICATIONS
VTTI = VTTO = VCC = 3.3 V, VEE = 0 V, RL = 50 , differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223 - 1, VIN = 1 V p-p differential, TA = 25C, unless otherwise noted. Table 2.
Parameter FIRST RANK WRITE CYCLE CS to WE Setup Time Address Setup Time Data Setup Time WE to CS Hold Time Address Hold Time Data Hold Time WE Pulse Width SECOND RANK UPDATE CYCLE CS to UPD Setup Time UPD to CS Hold Time Output Enable Output Switch Output Disable UPD Pulse Width TRANSPARENT WRITE AND UPDATE CYCLE Output Enable Output Toggle Output Disable SECOND RANK READBACK CYCLE CS to RE Setup Time RE to CS Hold Time ADDR from RE DATA from RE Access Time RE to Read Disable ASYNCHRONOUS RESET Output Disable RST Pulse Width Symbol tCSW tASW tDSW tCHW tAHW tDHW tWP tCSU tCHU tUOE tUOT tUOD tUW tWOE tWOT tWOD tCSR tCHR tRHA tRDE tAA tRDD tTOD tTW 0 0 5 15 15 50 10 10 30 Min 0 0 1 0 0 0 10 0 0 20 10 20 10 35 25 25 50 45 45 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
25
Rev. 0 | Page 4 of 20
AD8156 TIMING DIAGRAMS
CS
WE
A[3:0]
D[3:0]
tCSW tASW tWP tDSW tAHW
tCHW
06305-002
tDHW
Figure 2. First Rank Write Cycle
CS
UPD
OUTxN/P ENABLE
OUTxN/P DISABLE
OUTxN/P TOGGLE
tCSU tUOE tUOD
tUW
tCHU
06305-003
tUOT
Figure 3. Second Rank Update Cycle
Rev. 0 | Page 5 of 20
AD8156
CS
UPD
WE
OUTxN/P ENABLE
OUTxN/P DISABLE
OUTxN/P TOGGLE
tWOE tWOD tWOT
tWHU
06305-004
Figure 4. Transparent Write and Update Cycle
CS
RE
ADDR[3:0]
ADDR1
ADDR2
DATA[3:0]
DATA1
DATA2
tCSR
tRDE
tAA
tRHA
06305-005
06305-006
tCHR tRDD
Figure 5. Second Rank Readback Cycle
RST
OUTxN/P DISABLE
tTOD tTW
Figure 6. Asynchronous Reset
Rev. 0 | Page 6 of 20
AD8156 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VCC to VEE VTTI VTTO Internal Power Dissipation1 Input Voltage Logic Input Voltage Storage Temperature Range Junction Temperature Lead Temperature Range
1
Rating 3.6 V VCC + 0.6 V VCC + 0.6 V 1.92 W VCC + 0.6 V VEE - 0.3 V < VIN < VCC + 0.6 V -65C to +125C 150C 300C
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Package Type 49-Ball CSP_BGA JA 65 JC 28 Unit C/W
ESD CAUTION
Specification for TA = 25C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 7 of 20
AD8156 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
7
VCC
6
IN0P
5
IN0N
4
VTTI
3
IN1P
2
IN1N
1
VEE
A
OUT0P
VCC
MODE
VEE
D3
VEE
IN2P
B
OUT0N
CS
WE
RST
D2
D0
IN2N
C
VTTO
VCC
UPD
VEE
D1
VEE
VTTI
D
OUT1P
VCC
RE
A3
A1
A0
IN3P
E
OUT1N
VEE
VEE
VEE
A2
VCC
IN3N
F
VEE
OUT2P
OUT2N
VTTO
OUT3P
OUT3N
VCC
G
Figure 7. Pin Configuration (Bottom View)
Table 5. Pin Function Descriptions
Pin No. A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 Mnemonic VEE IN1N IN1P VTTI IN0N IN0P VCC IN2P VEE D3 VEE MODE VCC OUT0P IN2N D0 D2 RST WE CS OUT0N VTTI VEE D1 VEE Description Negative Supply. High Speed Input Complement. High Speed Input. Input Termination Supply. High Speed Input Complement. High Speed Input. Positive Supply. High Speed Input. Negative Supply. Input Address Pin (MSB). Negative Supply. Mode Select Pin. Positive Supply. High Speed Output. High Speed Input Complement. Input Address Pin (LSB). Input Address Pin. Reset/Disable Outputs. First Bank Write Enable. Chip Select Enable. High Speed Output Complement. Input Termination Supply. Negative Supply. Input Address Pin. Negative Supply. Pin No. D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 Mnemonic UPD VCC VTTO IN3P A0 A1 A3 RE VCC OUT1P IN3N VCC A2 VEE VEE VEE OUT1N VCC OUT3N OUT3P VTTO OUT2N OUT2P VEE Description Second Bank Write Enable. Positive Supply. Output Termination Supply. High Speed Input. Address Pin (LSB). Address Pin. Address Pin (MSB). Second Bank Read Enable. Positive Supply. High Speed Output. High Speed Input Complement. Positive Supply. Address Pin. Negative Supply. Negative Supply. Negative Supply. High Speed Output Complement. Positive Supply. High Speed Output Complement. High Speed Output. Output Termination Supply. High Speed Output Complement. High Speed Output. Negative Supply.
Rev. 0 | Page 8 of 20
06305-007
AD8156 TYPICAL PERFORMANCE CHARACTERISTICS
VTTI = VTTO = VCC = 3.3 V, VEE = 0 V, RL = 50 , differential output swing = 800 mV, ac-coupled, data rate = 6.25 Gbps, PRBS 223 - 1, VIN = 1 V p-p differential, TA = 25C, unless otherwise noted.
200mV/DIV
06305-008
200mV/DIV
50ps/DIV
50ps/DIV
Figure 8. Input Eye Diagram at 3.2 Gbps,10" FR4
Figure 11. Output Eye Diagram at 3.2 Gbps, 10" FR4, Optimal EQ
200mV/DIV
200mV/DIV
06305-009
50ps/DIV
50ps/DIV
Figure 9. Input Eye Diagram at 3.2 Gbps, 40" FR4
Figure 12. Output Eye Diagram at 3.2 Gbps, 40" FR4, Optimal EQ
200mV/DIV
06305-010
200mV/DIV
25ps/DIV
25ps/DIV
Figure 10. Input Eye Diagram at 6.25 Gbps, 10" FR4
Figure 13. Output Eye Diagram at 6.25 Gbps, 10" FR4, Optimal EQ
Rev. 0 | Page 9 of 20
06305-013
06305-012
06305-011
AD8156
200mV/DIV
06305-014
200mV/DIV
25ps/DIV
25ps/DIV
Figure 14. Input Eye Diagram at 6.25 Gbps, 40" FR4
35 30
Figure 17. Output Eye Diagram at 6.25Gbps, 40" FR4, Optimal EQ
35 30
DETERMINISTIC JITTER (ps p-p)
DETERMINISTIC JITTER (ps)
6.25Gbps 25 20 15 10 5 0 -40
25 20 15 10 3.2Gbps
06305-015
6.25Gbps
0
0
0.5
1.0
1.5
2.0
2.5
-20
0
20
40
60
80
DIFFERENTIAL INPUT (V p-p)
TEMPERATURE (C)
Figure 15. Deterministic Jitter vs. Input Signal Level (No EQ)
35 30
DETERMINISTIC JITTER (ps p-p)
Figure 18. Deterministic Jitter vs. Temperature (Optimal EQ, 20" FR4)
35 30 25
25 20 15 10 5 0 0 1 2 3 4 5 6 7 INPUT DATA RATE (Gbps) DETERMINISTIC JITTER
EQ GAIN (dB)
20 15 10 5 0 0.1
06305-016
1 FREQUENCY (GHz)
10
Figure 16. Deterministic Jitter vs. Data Rate (No EQ)
Figure 19. Input EQ Gain vs. Frequency
Rev. 0 | Page 10 of 20
06305-020
06305-019
5
06305-017
AD8156
50 45 DETERMINISTIC JITTER (ps p-p) 40 EYE HEIGHT (mV) 35 30 25 20 15 10 5 0 3.0 3.1 3.2 3.3 VCC (V) 3.4 3.5
06305-022 06305-024
800 700 600 500 400 300 200 100 0
3.6
0
1
2
3
4
5
6
7
8
9
DATA RATE (Gbps)
Figure 20. Deterministic Jitter vs. VCC
50 45
DETERMINISTIC JITTER (ps p-p)
Figure 22. Eye Height vs. Data Rate
40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
06305-023
4.0
OUTPUT TERMINATION VOLTAGE (V)
Figure 21. Deterministic Jitter vs. Output Termination Voltage
Rev. 0 | Page 11 of 20
AD8156 TEST CIRCUIT
50 2 CABLES 2 50 2 CABLES 2 AC-COUPLED EVALUATION BOARD IN0P/N OUT0P/N OUT1P/N OUT2P/N OUT3P/N 2 2 2
06305-021
AD8156
DATA OUT PATTERN GENERATOR
FR4 TEST BACKPLANE
2
50 CABLES
2 50 HIGH SPEED SAMPLING OSCILLOSCOPE
IN1P/N DIFFERENTIAL STRIPLINE TRACES 8mils WIDE, 8mils SPACE, AND 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 10", 20", 30", AND 40" IN2P/N IN3P/N
*SINGLE-ENDED REPRESENTATION
50
50
50
Figure 23. AD8156 Test Circuit
Rev. 0 | Page 12 of 20
AD8156 THEORY OF OPERATION
The AD8156 is a 4 x 4 crosspoint switch with programmable input equalization and programmable output current levels. It can be used as a nonblocking and fully programmable 4 x 4 crosspoint switch, or as a dual 2 x 2 protection switch with fast channel switching. Each lane can run at any rate from dc to 6.25 Gbps independent of the other lanes. In 4 x 4 mode, the user writes the control data to double-latched memory cells through a simple CPU interface. Connectivity, individual output disables, output current level, and input equalization are all individually programmable. Broadcast addresses can be used to simultaneously program the functionality of all channels. A global reset disables the part and resets all equalizers and output current levels to their default states. A chip select pin can be used in applications where a single bus is controlling multiple switches. When in dual 2 x 2 mode, the part functions as two individual 2 x 2 switches whose connectivity is asynchronously controlled by the D3 to D0 pins, and output enable is controlled by the A3 to A0 pins. The dual 2 x 2 mode allows for sub-10 ns output channel switching or output enable. Output swing control and input equalization cannot be controlled in dual 2 x 2 mode because all the data and address pins are used as asynchronous control pins. However, settings are retained when switching modes, so the user can set the desired swing and input equalization settings in 4 x 4 mode on startup and then switch to dual 2 x 2 mode. The user can switch at will between 4 x 4 mode and dual 2 x 2 mode by toggling the MODE pin. When switching from 4 x 4 mode to dual 2 x 2 mode, EQ and output current settings are retained, but the output connectivity control is instantly switched to the asynchronous interface of A[3:0] and D[3:0]. To have uninterrupted data flow when switching from 4 x 4 mode to dual 2 x 2 mode, the address and data pins should be set into the desired states for dual 2 x 2 mode before changing the MODE pin. When switching from dual 2 x 2 mode to 4 x 4 mode, EQ and the output current settings are also retained, but the connectivity specified by the values of A[3:0] and D[3:0] when MODE went low are retained in memory. Until some other connectivity is set using the 4 x 4 control interface, the last dual 2 x 2 mode settings are stored in memory. If desired for verification, the value of the second bank of latches can be read back by pulling RE low. When RE is low, Data Pin D3 to Data Pin D0 are driven by the chip. The timing of this operation is shown in Figure 5. Because the interface is entirely asynchronous, the only limitation on the timing of the read cycle is that each period must be a minimum of 15 ns.
Connectivity Control
Connection between an output and an input is set by addressing a specific output and connecting it to an input. Each output has a disable bit. Table 10 shows how to set the crosspoint connectivity.
Output Current Control
Output current is controlled by addressing a specific output and choosing the output current. The output current is equal to 2 mA + (2 mA x D[3:0]) For example, the default code for D[3:0] is b0111. Therefore, the output current level is 2 mA + (2 mA x 7) = 16 mA. Table 11 and Table 13 show how to set the output current levels.
Input Equalization Control
Input equalization is set per input lane. The equalization is set in ~1.53 dB steps, from 0 dB to 23 dB of equalization at 3.125 GHz (roughly corresponding to a 6.25 Gbps bit rate). The amount of equalization is
gain( f ) = f D[3:0] x 40 log 10 15 0.83 GHz
A value of 0000 disables the equalizer, saving power.
Global Setting
By writing to one of three broadcast addresses, the user can set all connectivity, output current, or input equalization settings to the same value. Broadcast addresses are controlled similarly to other control addresses. See Table 12, Table 13, and Table 14 for broadcast mode programming.
DUAL 2 x 2 MODE
Pulling the MODE pin high puts the AD8156 in dual 2 x 2 mode. In this mode, the part is asynchronously controlled by the address and data pins, A[3:0] and D[3:0], respectively. In dual 2 x 2 mode, the switch is configured as two individual 2 x 2 switches, and each output can be individually disabled. OUT0 and OUT1 can be connected to either IN0 or IN1, and OUT2 and OUT3 can connect to either IN2 or IN3. There are no connectivity options in dual 2 x 2 mode to connect OUT0/OUT1 to IN2/IN3, or OUT2/OUT3 to IN0/IN1. In dual 2 x 2 mode, input equalization and output level settings are not accessible. If these functions are needed, the user should program these functions in 4 x 4 mode and then return to dual 2 x 2 mode. Output swing and equalization settings are retained from 4 x 4 mode to dual 2 x 2 mode. Readback is not available in dual 2 x 2 mode.
4 x 4 MODE
Pulling the MODE pin low puts the AD8156 in 4 x 4 mode. In this mode, the chip is controlled by the values stored in the onchip memory. This memory is organized as two banks of latches; the second bank controls the chip, and the first bank allows the next set of configuration data to be written while the chip is operating based on the second bank data. To write to the first bank of memory, the user sets data and address to the desired states and pulls WE low. This writing process is repeated until all desired configuration data is stored in the first bank of latches, and then the chip configuration is simultaneously updated by pulling UPD low.
Rev. 0 | Page 13 of 20
AD8156
When in dual 2 x 2 mode, the A[3:0] and D[3:0] pins set the AD8156 configuration state when CS is low. This configuration method allows the user to have multiple AD8156s share the control bus while each device has its own dedicated CS control signal.
INPUT RECEIVERS IN0P/N INPUT EQUALIZATION EQ 2x2 SWITCH IN1P/N IN2P/N EQ EQ 2x2 SWITCH OUT1P/N OUT2P/N
* * * *
AD8156
Peak gain of 23 dB at 3.125 GHz (~6.25 Gbps) Equalizes more than 40" of typical FR4 backplane with associated connectors and vias at all speeds 0.10 UI p-p residual deterministic jitter typ @ 3.125 Gbps 0.15 UI p-p residual deterministic jitter typ @ 6.25 Gbps
OUTPUT DRIVERS OUT0P/N
IN3P/N VCC MODE
EQ
OUT3P/N
06305-008
As with all equalizers, the gain setting is the key. The ideal method of choosing the proper gain setting is to run the equalizer with the channel, and choose the setting with minimum jitter. If this process is not possible or is too time consuming for the number of channels required, the loss of the channel at 3.125 GHz should be measured. The best equalizer setting is usually 2 dB to 4 dB more than the loss at 3.125 GHz. Using the 40 dB slope of the equalizer gain, the gain at other frequencies can be calculated based on the peak gain at 3.125 GHz. The formula to use is
gain( f ) = f D[3:0] x 40 log 10 15 0.83 GHz
Figure 24. AD8156 in Dual 2 x 2 Mode
INPUT EQUALIZATION
The AD8156 input equalization is an active scheme that is fully linear over all operating ranges. The useful range of equalization covers dc to 3.125 GHz frequencies or dc to 6.25 Gbps data rates. Other key features include: * * 15 steps of gain, linear in dB, programmable through the 4 x 4 control interface Gain has a 40 dB per decade slope
where f is the fundamental frequency of the data, or the data rate divided by 2 (that is, 6.25 Gbps f = 3.125 GHz). Performance of the equalizer is heavily dependent on the channel used. Operation at high speeds depends on features such as dielectric used (for example, FR4, Nelco3000, or Rogers), connector quality, via stub length, and routing geometry and topology.
Rev. 0 | Page 14 of 20
AD8156 CONTROL INTERFACE DESCRIPTION
The control interface for the AD8156 consists of a set of address, data, and several control pins. All control pins are active low. The control interface is level sensitive. all outputs are connected but disabled. RST overrides all of the other control pins.
CS Pin
The chip select pin, an active low signal, facilitates multiple chip address decoding. All control signals, except the reset signal, are ignored when CS is pulled high. The pin disables the control signals and does not affect operation of the chip. CS does not power down any of the latches, preserving any data programmed in the latches.
CONTROL PINS
All control pins on the chip are level-sensitive, not edge-triggered. The preferred programming method is to assert the data and address pins to their desired configuration, wait one control bit period, then pull WE low to write to the first bank of registers. After one control bit period, WE is pulled high. After an additional control bit period, the address and data pins can be set to their next values, and the cycle repeats. Using this method, each write takes three control bit periods. After the first bank of registers is programmed, UPD is pulled low, which transfers the data from the first bank of latches to the second bank of latches. When UPD is pulled low, the full chip updates, regardless of the status of the address, data, WE, or RE pins. Writing to the part while UPD is pulled low writes through the first bank of registers and into the second bank, immediately affecting the connectivity and output current of the part. It is recommended that the user write to the first bank with one data bit cycle, and subsequently activate the UPD pin low, because data and address pin skews presented to the part can lead to errors when writing through both banks simultaneously. If skews are properly controlled, a transparent write can allow a very quick change of states in 4 x 4 mode.
MODE Pin
The MODE pin sets the part in 4 x 4 mode or dual 2 x 2 mode. Pulling MODE low sets the part in 4 x 4 mode, and pulling MODE high sets the part in dual 2 x 2 mode. In dual 2 x 2 mode, the WE, RE, and UPD pins are unused.
WE Pin
This pin is the write enable to the first bank of registers. Forcing WE to logic low allows the data on the D[3:0] pins to be stored in the first bank of latches for the function specified by A[3:0]. The WE pin must be returned to logic high state before changing the other pins after a write cycle to avoid overwriting the first bank data.
UPD Pin
This pin is the write enable to the second bank of registers. Forcing UPD to logic low transfers the data stored in all first bank latches to the second bank latches, which is the active set of registers. The chip functions update during this operation.
RST Pin
At any time, a reset pulse to RST can be applied to the control interface to globally reset all first and second bank latches to their default values. The device has an internal power-on reset circuit, but it is recommended that RST be held low during power-up. The default values for the chip include disabling all outputs, turning off equalization, and setting output current code to the default, b0111 (16 mA). The default connection is the buffer state, or IN0 OUT0, IN1 OUT1, IN2 OUT2, IN3 OUT3; Table 6. Basic Control Pin Functions
RST 1 0 1 1 1 1 1 1 CS 1 x 0 0 0 0 0 0 MODE x x 0 0 0 0 0 1 WE x x 1 0 1 1 0 x RE x x 1 1 0 x x x UPD x x 1 1 1 0 0 x Function
RE Pin
This pin is the read enable for the second bank of registers. Forcing RE to logic low enables the on-chip drivers to drive the bidirectional D[3:0] pins. The on-chip drivers are only intended to drive high impedance loads, so any external drivers of D[3:0] must be disabled when RE is low.
Control Interface Disabled. Prior settings are stored, and the chip is run based on the configuration data stored (in 4 x 4 mode) or set (in dual 2 x 2 mode) previously. Global Reset. Disables all outputs and equalizers. Output current code set to 0111 (16 mA). 4 x 4 Mode. Address and data pins are ignored (values in the AD8156 memory control connectivity, output current, and EQ setting). Write Enable. Writes to the first bank of registers. Readback Enable. Reads back data on D[3:0] from the addressed latch (second bank of registers). Global Update. Transfers data from first bank of registers to second bank of registers (active set). Chip functions update. Transparent Write. Writes and updates simultaneously through first bank to the second bank of registers. Chip functions update. Dual 2 x 2 Mode. Address and data pins asynchronously control the device.
Rev. 0 | Page 15 of 20
AD8156
ADDRESS PINS, A[3:0] INPUTS
The AD8156 feature sets can be set port by port or globally. A[3:2] specify what is being programmed or read back when the part is being configured port by port. Connectivity, output current, equalization, or global programming features are chosen based on the values of A[3:2]. Similarly, A[1:0] address the port that is being programmed or read back. In global programming, A[1:0] serve a different function. Refer to Table 9 to Table 15 for programming examples.
DATA PINS, D[3:0] INPUTS/OUTPUTS
In readback mode, the D[3:0] pins are low impedance outputs indicating the stored values in the memory to be read. The readback drivers are designed to drive high impedances only, so external drivers connected to D[3:0] must be disabled during readback mode.
CONTROL INTERFACE LEVELS
The AD8156 control interface shares the data path supply pins, VCC and VEE. The potential between the positive logic supply VCC and the negative supply VEE must be at least 3.0 V and no more than 3.7 V. Regardless of supply, the logic threshold is approximately one-half the supply range, allowing the interface to be used with most LVCMOS- and LVTTL-logic drivers.
Table 7. Dual 2 x 2 Mode Programming Table
Address A[3:0] Input A3 to Input A0 enable Output 3 to Output 0, respectively. 1 = Enables the output (for all A[3:0] inputs) 0 = Disables the output (for all A[3:0] inputs) Data D[3:0] Input D3 to Input D0 control the connectivity of Output 3 to Output 0, respectively. 0 = Input 2, 1 = Input 3 (for D2 and D3) 0 = Input 0, 1 = Input 1 (for D0 and D1)
Table 8. 4 x 4 Mode Programming Table
Mode Write/Read Connectivity and Disable Address A[3:0] 0 0 A1 A0 A1 and A0 determine which output is being programmed. 0 1 A1 A0 A1 and A0 determine which output is being programmed. 1000 Data D[3:0] 0 D2 D1 D0 D1 and D0 determine which input is connected to which output; D2 determines the enabled/disabled state of that output, with D2 = 1 (enable). When writing or reading, D3 is always 0. D3 D2 D1 D0 D0 to D3 binarily program the output current level/voltage swing with the output current = 2 mA + (2 mA x decimal (D[3:0])). 0 D2 D1 D0 D1 and D0 determine which input is connected to all of the outputs. D2 determines the enabled/disabled state of all outputs with D2 = 1 (enable). When writing or reading, D3 is always 0. D3 D2 D1 D0 D0 to D3 binarily program the output current level/voltage swing with the output current = 2 mA + (2 mA x decimal (D[3:0])). The value is written to all outputs. D3 D2 D1 D0 Data inputs D0 to D3 set the input equalization level where: Gain(f ) = D[3:0]/15 x 40 log10(f/0.83 GHz). D3 D2 D1 D0 D0 to D3 set the input equalization level, where: Gain(f ) = D[3:0]15 x 40 log10(f0.83 GHz).
Write/Read Output Current Level Broadcast Connectivity/Disable
Broadcast Output Current Level
1001
Broadcast EQ Setting
1011
Program EQ Setting
1 1 A1 A0 A1 and A0 determine which input is being programmed.
Rev. 0 | Page 16 of 20
AD8156 PROGRAMMING EXAMPLES
A[3:0]
D[3:0]
WE
UPD
Figure 25. Sample Timing Diagram for 4x4 Mode Programming Examples
DUAL 2 x 2 MODE (MODE PIN = 1) PROGRAMMING EXAMPLES
Table 9. Dual 2 x 2 Mode Programming
A3 1 1 1 1 0 0 1 Address Pins A2 A1 A0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 1 0 1 1 D3 0 1 0 1 x x 0 Data Pins D2 D1 x x x x 0 x 0 x x x 1 0 1 0 D0 x x x x x 1 1 Description A[3] = 1 enables OUT3. D[3] = 0 connects IN2 to OUT3. A[3] = 1 enables OUT3. D[3] = 1 connects IN3 to OUT3. A[3:2] = b11 enables OUT2 and OUT3. D[3:2] = b00 connects IN2 to both OUT2 and OUT3. A[3:2] = b11 enables OUT2 and OUT3. D[3:2] = b10 connects IN2 to OUT2 and connects IN3 to OUT3. A[1] = 1 enables OUT1. D[1] = 0 connects IN0 to OUT1. D[1:0] = b11 enables OUT0 and OUT1. D[1:0] = b11 connects IN1 to both OUT0 and OUT1. A[3:0] = b1111 enables all outputs. D[3:0] = b0101 connects IN2 to OUT3, IN3 to OUT2, IN0 to OUT1, IN1 to OUT0.
4 x 4 MODE (MODE PIN = 0) PROGRAMMING EXAMPLES
Table 10. Connectivity Programming, A[3:2] = b00
Address Pins A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 D3 0 0 0 0 Data Pins D2 D1 1 0 0 0 1 0 1 0 D0 0 0 1 0 Description A[1:0] = 0 selects OUT0. D2 = 1 enables OUT0. D[1:0] = 0 connects IN0 to OUT0. A[1:0] = 0 selects OUT0. D2 = 0 disables OUT0. D[1:0] = 0 connects IN0 to OUT0. A[1:0] = b10 selects OUT2. D2 = 1 enables OUT2. D[1:0] = b01 connects IN1 to OUT2. A[1:0] = b11 selects OUT3. D2 = 1 enables OUT3. D[1:0] = b00 connects IN0 to OUT3.
Table 11. Output Level Programming, A[3:2] = b01
A3 0 0 0 0 Address Pins A2 A1 A0 1 0 0 1 0 0 1 1 0 1 1 1 D3 0 1 1 0 Data Pins D2 D1 1 0 0 0 1 0 0 0 D0 0 0 1 0 Description (Output Current = 2 mA + (2 mA x D[3:0]) A[1:0] = 0 selects OUT0. D[3:0] = b0100 sets OUT0 current to 2 mA + (2 mA x 4) = 10 mA. A[1:0] = 0 selects OUT0. D[3:0] = b1000 sets OUT0 current to 2 mA + (2 mA x 8) = 18 mA. A[1:0] = b10 selects OUT2. D[3:0] = b1101 sets OUT2 current to 2 mA + (2 mA x 13) = 28 mA. A[1:0] = b11 selects OUT3. D[3:0] = b0000 sets OUT3 current to 2 mA + (2 mA x 0) = 2 mA.
Rev. 0 | Page 17 of 20
06305-009
AD8156
Table 12. Broadcast Connectivity Programming, A[3:0] = b1000
A3 1 1 1 Address Pins A2 A1 0 0 0 0 0 0 A0 0 0 0 D3 0 0 0 Data Pins D2 D1 1 0 1 1 0 1 D0 0 1 0 Description D2 = 1 enables all outputs. D[1:0] = b00 connects IN0 to all outputs. D2 = 1 enables all outputs. D[1:0] = b11 connects IN3 to all outputs. D2 = 0 disables all outputs. D[1:0] = b10 connects IN2 to all outputs, but all outputs are disabled.
Table 13. Broadcast Output Level Programming, A[3:0] = b1001
A3 1 1 1 Address Pins A2 A1 0 0 0 0 0 0 A0 1 1 1 D3 0 1 0 Data Pins D2 D1 1 0 1 0 0 0 D0 0 1 0 Description (Output Current = 2 mA + (2 mA x D[3:0]) D[3:0] = b0100 sets current of all outputs to 2 mA + (2 mA x 4) = 10 mA. D[3:0] = b1101 sets current of all outputs to 2 mA + (2 mA x 13) = 28 mA. D[3:0] = b0000 sets current of all outputs to 2 mA + (2 mA x 0) = 2 mA.
Table 14. Broadcast Equalization (EQ) Programming, A[3:0] = b1011
A3 1 1 1 Address Pins A2 A1 A0 0 1 1 0 1 1 0 1 1 D3 0 1 0 Data Pins D2 D1 1 0 1 0 0 0 D0 0 1 0 Description (Gain(f) = D[3:0]15 x 40 log10(f0.83 GHz)), assume f = 2.25 GHz D[3:0] = b0100 sets all input EQ = (4/15 x 40 log10(2.25 GHz/0.83 GHz)) = 4.6 dB. D[3:0] = b1101 sets all input EQ = (13/15 x 40 log10(2.25 GHz/0.83 GHz)) =14.95 dB. D[3:0] = b0000 sets all input EQ = (0/15 x 40 log10(2.25 GHz/0.83 GHz)) = 0 dB.
Table 15. Individual Input EQ Programming, A[3:2] = b11
A3 1 1 1 1 Address Pins A2 A1 A0 1 0 0 1 1 1 0 1 1 1 0 1 D3 0 1 1 0 Data Pins D2 D1 1 0 1 1 0 0 1 0 D0 0 1 1 0 Description (Gain(f) = D[3:0]15 x 40log10(f0.83 GHz)), assume f = 2.25 GHz A[1:0] = b00 selects IN0. D[3:0] = b0100 sets EQ = (4/15 x 40 log10(2.25 GHz/0.83 GHz)) = 4.6 dB. A[1:0] = b01 selects IN1. D[3:0] = b1101 sets EQ = (13/15 x 40 log10(2.25 GHz/0.83 GHz)) = 14.95 dB. A[1:0] = b10 selects IN2. D[3:0] = b1111 sets EQ = (15/15 x 40 log10(2.25 GHz/0.83 GHz)) = 17.25 dB. A[1:0] = b11 selects IN3. D[3:0] = b0000 sets EQ = (0/15 x 40 log10(2.25 GHz/0.83 GHz)) = 0 dB.
Rev. 0 | Page 18 of 20
AD8156 OUTLINE DIMENSIONS
8.20 8.00 SQ 7.80 A1 CORNER INDEX AREA
7 6 5 4 3 2 1 A
BALL A1 PAD CORNER TOP VIEW 6.00 BSC SQ
B C D E F G
*1.85 1.71 1.50
DETAIL A
1.00 BSC 0.25 MIN
BOTTOM VIEW
DETAILA
*1.31 1.21 1.10 COPLANARITY 0.20
0.70 0.60 0.50 BALL DIAMETER
SEATING PLANE
*COMPLIANT WITH JEDEC STANDARDS MO-192-ABB-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 26. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-49-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8156ABCZ 1 AD8156-EVALZ1
1
Temperature Range -40C to +85C
Package Description 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board
012006-0
Package Option BC-49-3
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
AD8156 NOTES
(c) 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06305-0-5/07(0)
Rev. 0 | Page 20 of 20

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